As the density of integrated circuits increases, it becomes necessary to shrink the dimensions of NMOS and PMOS transistors. Proper scaling of NMOS and PMOS transistors typically requires that the operating voltage be decreased as the gate oxide thickness is shrunk. Otherwise, the electric field will become too large in the gate oxide and, consequently, the gate oxide will eventually fail.
On the other hand, if the operating voltage is decreased, the device will no longer be compatible with most of the current packaged integrated circuits which operate at a standard voltage. For, instance, most circuits using CMOS transistors with gate lengths of 0.8 microns or more operate at 5.0 V. When the gate length in decreased to 0.5 microns and the gate oxide thickness to 90-120 .ANG., the voltage is lowered to 3.3 V in order to maintain reliability of the gate oxide. Thus, a device is needed that has input/output peripheral sections that operate at 5.0 V so that the device may be used in systems using other chips operating at 5.0 V while allowing other portions of the device to operate at 3.3 V. The same problem occurs when the gate length is reduced from 0.5 .mu.m to 0.35 .mu.m or 0.25 .mu.m. At 0.35 .mu.m, the voltage is reduced to 2.5 V or lower in order to maintain the integrity of the gate oxide.
One method that has been used to overcome this problem uses longer gate lengths in the input/output CMOS transistors in order to minimize the hot carrier stress problem. However, gate insulator reliability may still be a problem due to the large electric field in the gate insulator.
Another method uses a thicker gate oxide for the input/output sections. This lowers the electric field in the high voltage CMOS transistors. However, this method requires a resist to be patterned on the gate oxide to remove the oxide from one portion of the chip and then strip the resist and grow the second gate oxide of a different thickness. As a result, defects and contamination may occur in the gate oxide.
Another approach uses two polysilicon layers. One polysilicon layer is placed over a first gate of one thickness. Next, a second gate oxide is grown and another polysilicon layer is deposited over the second gate oxide. This process however, adds to many additional process steps.